1. Field of the Invention
The present invention relates generally to a level shifter and level shifting method for high-speed operations and which may reduce power consumption in semiconductor devices.
2. Description of the Related Art
As process technologies develop, operating voltages of a semiconductor device and internal circuit therein continuously decrease. In addition, the internal operating voltage of the semiconductor device has been reduced in order to increase operating speed and to reduce power consumption of the semiconductor device. However, some semiconductor devices or some internal circuits therein require a high voltage due to operating characteristics. Therefore, when a semiconductor device and/or internal circuits therein which operate with a high operating voltage are used in conjunction with another semiconductor device and/or internal circuits therein that do not operate using a high voltage, a voltage interface is needed between the semiconductor devices and/or the internal circuits.
For a semiconductor device operating at a high speed, it is more difficult to implement a level shifter to shift a low level of voltage to a high level of voltage, than it is to level shift from a high level of voltage to a low level of voltage. Also, the conventional level shifter performing a voltage shift from a low-to-high voltage has problems including reduced operating speed, reduced duty ratio, and increased power consumption caused by leakage current.
FIG. 1 is a circuit diagram of a conventional level shifter. The level shifter includes two inverters IV1 and IV2, two NMOS transistors N1 and N2, and two PMOS transistors P1 and P2. In FIG. 1, Vin refers to an input signal, Vout refers to an output signal, V1 refers to a first supply voltage, V2 refers to a second supply voltage higher than the first supply voltage, and Vss refers to a ground voltage.
In operation, when the input signal Vin has the level of the ground voltage Vss, the NMOS transistor N1 is turned on and the NMOS transistor N2 is turned off. With NMOS transistor N1 on and NMOS transistor N2 off, the voltage at node T1 becomes the level of the ground voltage Vss and PMOS transistor P2 is turned on. With PMOS transistor P2 on, the voltage at a node T2 becomes the level of the second supply voltage V2, PMOS transistor P1 is turned off and the output signal Vout has the level of the ground voltage Vss.
When the input signal Vin has the level of the first supply voltage V1, the NMOS transistor N1 is turned off and the NMOS transistor N2 is turned on, so that the voltage at node T2 is the level of the ground voltage Vss and thus the PMOS transistor P1 is turned off. Therefore, the voltage at node T1 becomes the ground voltage Vss and the PMOS transistor P2 is turned off. Here, since the voltage at node T2 becomes the ground voltage Vss, the output signal Vout has the level of the second supply voltage V2.
FIG. 2 is a timing diagram illustrating in detail the operation of the conventional level shifter shown in FIG. 1. In FIG. 2, Vin refers to the input signal, Vout refers to the output signal, T1 refers to the voltage at the node T1, and T2 refers to the voltage at the node T2.
Referring to FIG. 2, when the input signal Vin shifts from the level of the ground voltage Vss to the level of the first supply voltage V1, the NMOS transistor N1 is turned off and the NMOS transistor N2 is turned on. Therefore, the voltage at the node T2 decreases due to the current discharged by NMOS transistor N2. When the voltage at the node T2 decreases to where it becomes equal or less than a given voltage which may be set in advance (V2-Vth, where Vth is a threshold voltage of a PMOS transistor), the PMOS transistor P1 is turned on and thus the voltage at the node T1 begins to rise. When the voltage at the node T1 exceeds V2-Vth, the PMOS transistor P2 is turned off. As a result, when the voltage at the node T2 drops below V2-Vth, the voltage level of the output signal Vout shifts (increases) to the level of the second supply voltage V2 via a second inverter IV2.
Still referring to FIG. 2, when the input signal Vin shifts from the level of the first supply voltage V1 to the level of the ground voltage Vss, the NMOS transistor N1 is turned on and the NMOS transistor N2 is turned off. Therefore, the voltage at node T1 decreases. Once the voltage at the node T1 drops below V2-Vth, the PMOS transistor P2 is turned on, and the voltage at node T2 begins to increase. As a result, the output signal Vout shifts (decreases) to the level of the ground voltage Vss.
The conventional level shifter shown in FIG. 1 has problems of leakage current, reduced operating speed due to two steps of gate delay, and increased power consumption. For example, if the input signal Vin shifts from the level of the ground voltage Vss to the level of the first supply voltage V1, both the PMOS transistor P2 and the NMOS transistor N2 are turned on at the same time from a point in time when the input signal Vin shifts to the point of time when the voltage at node T1 increases and thus the PMOS transistor P2 is turned off. Therefore, leakage current occurs, flowing through the PMOS transistor P2 and the NMOS transistor N2, which are both on at the same time.
In another example, if the input signal Vin shifts from the level of the first supply voltage V1 to the level of the ground voltage Vss, both the PMOS transistor P1 and the NMOS transistor N1 are turned on at the same time from a point in time when the input signal Vin shifts to the point of time when the voltage at node T2 increases and thus the PMOS transistor P1 is turned off. Therefore, leakage current flows through the PMOS transistor P1 and the NMOS transistor N1, since both are both on. This generation of leakage currents in the level shifter slows operating speed and increases power consumption of the level shifter.
The conventional level shifter has two steps of gate delay for a level shift operations between input and output signals. For example, when the input signal Vin shifts from the level of the ground voltage Vss to the level of the first supply voltage V1, the voltage at node T2 decreases to turn on the PMOS transistor P1 and thus the voltage at node T1 increases to turn off PMOS transistor P2. Therefore, the conventional level shifter of FIG. 1 needs time for two steps of gate delay. Similarly, when the input signal Vin shifts from the level of the first supply voltage V1 to the level of the ground voltage Vss, the conventional level shifter again needs time for two steps of gate delay, since the voltage at node T1 decreases to turn on PMOS transistor P2 and then the voltage at the node T2 increases to turn off PMOS transistor P1. The time required for two steps of gate delay is another factor slowing operating speed of the conventional level shifter.
Due to the above factors slowing operation, the duty ratio of the conventional level shifter deteriorates substantially at frequencies generally above 500 MHz. Further, the conventional level shifter has substantial problems operating at frequencies above 1 GHz.
To explain the deterioration of the duty ratio, the point of time when the voltage at node T2 begins to decrease to the ground voltage Vss depends on only the NMOS transistor N2. On the other hand, the point of time when the voltage at node T2 begins to increase to the second supply voltage V2 depends on the time when the voltage at the node T1 decreases by the NMOS transistor N1 and thus when the PMOS transistor P2 is turned on. Consequently, there is a short time gap between the former and latter points of time. As a result, the duty ratio deteriorates considerably when the conventional level shifter operates at a high speed. In addition, a uniform duty ratio cannot easily be maintained.
In addition, PMOS transistors are generally designed to be larger than NMOS transistors. However, the conventional level shifter shown in FIG. 1 can only operate when the electric charges discharged from nodes T1 and T2 by the NMOS transistors N1 and N2 are greater than the electric charges charged to the nodes T1 and T2 by PMOS transistors P1 and P2. Accordingly, for the conventional level shifter the NMOS transistors are designed to be larger than the PMOS transistors, which renders the level shifter incapable of normal operations under certain conditions, such as a low supply voltage.